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Energy Initiative

Low Power Circuits and Systems (LPC&S) Laboratory

Dr. Alexander Fish's Low Power Circuits and Systems (LPC&S) Laboratory has become a major research entity in Israel. Its main contributions are in the area of energy efficient digital and memory circuits
1.    Ultra low Voltage Static Random Access Memories (SRAMs)
Recently the group designed, fabricated and successfully measured two ultra low power low voltage SRAM arrays in 40nm process. This was the first 40nm chip in Israel developed by an academic team. The SRAM bitcells are based on a novel internal supply feedback mechanism, which allows full functionality under global and local process variations at nominal and low voltages, as low as 250mV.
2.   Low Voltage digital circuits operated in the sub/near threshold region

LPC&S group members have designed, fabricated and successfully measured an 80nm sub/near threshold test chip. The test chip included hundreds of test structures, starting from single transistors to complex cryptographic circuits. It was shown that our designed circuits were fully operational at supply voltages as low as 300mV and allowed x10-x20 power reduction. A proposal has been put forth for a novel low voltage Dual Mode Logic (DML), which provides the option to control system performance on-the-fly and thus support applications in which a flexible workload is required. The efficiency of DML has been proven through theoretical analysis, simulations and measurements from a test chip.
3.   Energy efficient CMOS image sensors
In this project new techniques for reduction of power dissipation in current state-of-the-art CMOS "smart" image sensors are developed. Recently, LPC&S lab members have developed the following methodologies for low power CMOS image sensors:
- Adaptive Bulk Biasing Technique, which allows both leakage power reduction and performance improvement in image sensors. The proposed concept was proven by measurements of 180nm and 80nm test chips.
- Low Voltage CMOS image sensors –a CMOS image sensor was designed which was operated from a low voltage supply (around 500mV). Theoretical analysis has been performed and currently measurements of a 180nm test chip are in progress.  
For more information see our publications at: